The field of the invention is manufacture of microelectronic devices, especially relating to damascene processing and methods of deposition of etch resistant material.
Currently, aluminum and aluminum alloys are the most commonly used conductive materials in electronic interconnections in an integrated circuit. Aluminum alloys generally have many desirable properties, including relatively strong adhesion to silicon, and comparably low resistivity. However, as device miniaturization proceeds, the resistivity of aluminum becomes non-negligible and begins to contribute significantly to the resistance-capacitance (RC) time delay of a circuit. With even more progressive miniaturization, the use of aluminum will become increasingly problematic due to electromigration, stress-induced void formation, and current density limitations. Therefore, in view of the continuing decrease in size of elements in integrated circuits, a growing interest has developed to find alternative conductive materials in interconnect structures.
One especially promising alternative material is copper and copper alloys because of their greater robustness and higher electrical conductivity. For example, copper has an approximately 40% lower resistivity than aluminum, and has fewer reliability problems such as electromigration, etc. However, copper is more difficult to etch than aluminum alloys, and generally can not be processed in a conventional metallization process in which a metal layer is deposited on a substrate and etched to form conductive lines, and in which the space between the lines is subsequently filled with a line dielectric. To circumvent at least some of the problems associated with the use of copper in the fabrication of interconnect structures, a new process for the manufacture of interconnects has been developed, also known as damascene process.
In a typical damascene process, a line pattern is etched in the surface of a dielectric layer, and the trenches formed in this manner are filled with copper by electroplating, electroless plating, or sputtering. After the copper is deposited onto the entire surface, a chemical-mechanical planarization (CMP) step is employed to remove excess copper, and to planarize the wafer for subsequent processing steps. This process is typically repeated several times to form vias and lines in a multi-layer interconnect structure.
To further improve the damascene process, via and line formation can be integrated into a single process, which is then called dual damascene process. In the dual damascene process a via dielectric layer is laid down onto a substrate, and the via dielectric layer is subsequently coated with a patterned etch stop layer, whereby voids in the etch stop layer correspond to positions of vias that will be etched into the via dielectric. In a next step a line dielectric is deposited onto the etch stop layer, which in turn is coated with a patterned hard mask layer that defines the traces of the lines. In a following step via and line traces are formed, whereby the line trenches are etched into the line dielectric until the etchant reaches the etch stop layer. In positions where there is no etch stop layer, the etching process continues through the via dielectric to form a via. As in the damascene process, etched via and line traces are filled with copper (after applying a Ta(N) barrier layer and a Cu-seed layer) and a CMP step finishes the dual damascene process. A typical dual damascene process is described in U.S. Pat. No. 5,801,094 to Yew, T., et al, which is hereby incorporated by reference.
Although more efficient than the damascene process, the dual damascene process requires sequential deposition of additional layers of dielectric material with different etch selectivity. With respect to the deposition of the via and line dielectric, various relatively fast and efficient methods are known in the art to lay down the via and line dielectric material. However, due to the special chemical make up of the hard mask and the etch stop material, deposition is generally limited to chemical vapor deposition (CVD). CVD typically requires a separate production environment with reduced atmospheric pressure and relatively high temperatures, thereby at least partially limiting the choice of line and via dielectric to materials that are able to withstand such relatively harsh conditions. Furthermore, depending on the hard mask and the etch stop material, the CVD step is often time consuming, and usually adds additional cost to the production. A yet further disadvantage of known hard mask and etch stop materials is their relatively high dielectric constant (k-value). For example, typical hard mask and etch stop materials, including SiN, SiON, and SiO2 have undesirably high dielectric constants in the range of about 7-4, respectively.
An additional problem arises when multiple damascene structure layers are required. Since copper exhibits a relatively fast diffusion rate, a diffusion barrier is generally needed to separate copper traces of one damascene layer from the via dielectric of the next damascene layer. Diffusion barriers typically comprise tungsten, tantalum, or various nitrides or carbides, including titanium nitride, tungsten nitride, titanium carbide, or tantalum nitride, and are generally applied by chemical vapor deposition. Alternatively, a TixAlyNz or aluminum wetting layer can be deposited by CVD or physical vapor deposition (PVD) techniques as diffusion barrier, which is described in U.S. Pat. No. 5,939,788, hereby incorporated by reference. Laying down a barrier layer by CVD or PVD does allow for a relatively controlled deposition, however, additional production time and frequently substantial cost is added to the production of multilayer dual damascene structures.
Although the use of layered dielectric materials with different etch selectivity enables the integration of copper in the fabrication of microelectronic devices, known methods to deposit layered dielectric materials are often relatively expensive, or employ materials with a comparably high dielectric constant. Therefore, there is a need to provide improved compositions and methods for producing layered dielectric materials having different etch selectivity from one another.
The present invention is directed to electronic devices and related methods, wherein the electronic devices include a hard mask layer that is applied in a liquid phase to a line dielectric layer (preferably in a spin-on process), wherein the hard mask layer comprises a Sixe2x80x94N bond, and wherein the hard mask layer is densified such that etch rate of the hard mask layer is less than the etch rate of both the line dielectric layer and the dielectric layer. It is further contemplated that the hard mask layer, the line dielectric layer, the via dielectric layer, and a copper element form a dual damascene structure.
In one aspect of the inventive subject matter, the line dielectric layer comprises an inorganic low dielectric constant material, or an organic low dielectric constant material, preferably a polyarylene ether, a polyarylene, a polyimide, or a cyanate ester resin. Especially preferred materials for the hard mask layer include polyperhydrosilazanes such as (SiH2xe2x80x94NH)n, with n=between 2 and 2000.
In another aspect of the inventive subject matter, the hard mask layer is densified using a process selected from the group consisting of a furnace cure process, a rapid thermal anneal process, a hot plate anneal process, and an electron beam process. Further preferred damascene structures include a diffusion barrier that is applied in a liquid phase to the hard mask layer, and that comprises a Sixe2x80x94N bond.
Various objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the invention, along with the accompanying drawings in which like numerals represent like components.